1. Field of the Invention
The invention relates to a signal detecting system, and particularly to a memory error signal detecting system used in a computer apparatus.
2. Description of Related Art
When the server is tested, it is required for the operator to rely on the error log generated by the board management controller (BMC) to find the reason why the server can not operate normally Among a plurality of issues causing the server can not operate normally, one of the issues is that uncorrected memory errors occur in the memory, and when accumulated times that the uncorrected memory errors occur in the memory achieve to a predetermined value, the server can be restarted.
FIG. 1 is a schematic system block diagram of a conventional computer apparatus. Referring to FIG. 1, it simply shows the relationship of the central processing unit (CPU) 102 and the memory 104. When the CPU 102 reads the data stored in the memory 104, if uncorrected memory errors are found, the counter inside the CPU 102 will start to count the accumulated times that the uncorrected memory errors occur in the memory. When the accumulated times are equal to a predetermined value, the CPU 102 will pull a memory error signal CATERR down to a low voltage level from a high voltage level, and also pull a reset signal RST down to the low voltage level to restart the server.
Accordingly, in the conventional technology, if the operator wants to know whether restarting the server is due to too many uncorrected memory errors occurring in the memory, the operator can record the state of the memory error signal CATERR. In other words, if the server is restarted, and it is also found that the memory error signal CATERR is pulled down to the low voltage level in the BMC's error log, the operator will determine that this error is due to too many uncorrected memory errors occurring in the memory 104.
However, in the conventional technology, the determination is not exact. As shown in FIG. 1, a DC voltage VDD biases the memory error signal CATERR through the resistor 106. In other words, when the CPU 102 pulls the reset signal down to the low voltage level, thereby restarting the server, the DC voltage VDD also is turned off. At this time, the memory error signal CATERR is pulled down to the low voltage level. Accordingly, if the operator determines that whether too many uncorrected memory errors occur in the memory 104 simply based on that whether the memory error signal CATERR is pulled down to the low voltage level when the server is restarted, it is not exact. The operator can not confirm that the memory error signal CATERR pulled down to the low voltage level is due to the server restarted or too many uncorrected memory errors occurring in the memory 104. Accordingly, it will trouble the operator when he or she debugs the server. Taiwan patent number 1300654, filed on Jan. 4, 2006, disclosed a pulse single detection device.